Fabrication of transistors with a fully silicided gate electrode and channel strain

ABSTRACT

An integrated circuit includes one or more transistors on or in a semiconductor substrate. At least one of the transistors includes a gate electrode and source and drain structures. The gate electrode has a fully silicided gate electrode layer with a ratio of Ni:Si ranging from about 2:1 to about 3:1. The source and drain structures are located in openings of the substrate and adjacent to the gate electrode. The source and drain structures are filled with SiGe to produce stress in the transistor channel region.

TECHNICAL FIELD

The disclosure is directed, in general, to semiconductor devices, andmore specifically, to the manufacture of transistors having a fullysilicided gate (FUSI) electrode and strained channel, and to deviceshaving such transistors.

BACKGROUND

The continuing push to produce faster semiconductor devices with lowerpower consumption has resulted in device miniaturization. As part ofthese efforts, there is interest in the use metal gate electrodes and inproducing channel strain in transistors. The use of metal gates canavoid the depletion of gate charge carriers at the interface between thegate and gate dielectric, such as encountered when a polysilicon gateelectrode is biased to invert the channel. The production of strain canimprove carrier mobility in the channel region of semiconductorsubstrates.

Unfortunately, the manufacture of semiconductor devices having metalgates and channel strain are not without problems. The addition ofmanufacturing processes for metal gate into existing semiconductordevice manufacturing processes has been problematic. E.g., it has provendifficult to use a single metal with different work function incomplementary nMOS and pMOS transistors. Additionally, the incorporationof strain-producing materials into semiconductor substrates withoutcausing a high leakage current, and making electrical contacts to suchmaterials, has also been problematic. The integration of metal gates andchannel strain fabrication process into the same transistor using anefficient process presents additional challenges.

Accordingly, what is needed is a method for manufacturing semiconductordevices that integrates the manufacture of metal gate electrodes of theappropriate work function with a strained channel.

SUMMARY

The disclosure provides a method of manufacturing a semiconductordevice. The method comprises forming first and second gates, includingpatterning a silicon-containing layer on a semiconductor substrate. Thepatterned silicon-containing layer of the first gate, and firstsubstrate portions adjacent to the first gate, are etched simultaneouslyto form a first gate electrode opening and source and drain openings,respectively. The second gate and second substrate portions adjacent tothe second gate are masked. The method also comprises forming SiGesimultaneously in the first gate electrode openings and in the sourceand drain openings, wherein the second gate and the second substrateportions are masked. The SiGe is removed from an upper surface of thefirst gate to form a second gate electrode opening therein. A metal isdeposited simultaneously on the first and second gates to form a metallayer thereon. The first and second gates are annealed to form fullysilicided first and second gate electrodes. An amount of the metal at aninterface of the fully silicided gate electrode layer and an underlyinggate dielectric layer is greater than an amount of the metal at a secondinterface of the second fully silicided gate electrode layer and anunderlying second gate dielectric layer.

Another embodiment is method of manufacturing an integrated circuit thatcomprises forming one or more transistors on a semiconductor substrate,wherein at least one of the transistors is manufactured by steps thatinclude the above-described process. The transistor's manufacturefurther includes depositing a sacrificial layer on the substrate,wherein the first and second gates are covered by said sacrificiallayer, and uncovering upper surfaces of the first and second gates,wherein the SiGe-filled source and drain openings remained covered. Themethod also includes depositing a pre-metal dielectric layer on thesubstrate and inter-level dielectric layers on the pre-metal dielectriclayer and forming interconnects through one or more of the inter-leveldielectric layers to interconnect the at least one transistors to eachother, or to other transistors of the integrated circuit.

Another embodiment is an integrated circuit. The integrated circuitcomprises one or more transistors on or in a semiconductor substrate. Atleast one of the transistors includes a gate electrode and source anddrain structures. The gate electrode has a fully silicided gateelectrode layer with a ratio of Ni:Si ranging from about 2:1 to about3:1. The source and drain structures are located in openings of thesubstrate and adjacent to the gate electrode, wherein the source anddrain structures are filled with SiGe.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1 to 10 present cross-section views of selected steps in exampleimplementation of a method of fabricating a semiconductor deviceaccording to the principles of the present disclosure.

DETAILED DESCRIPTION

One embodiment of the disclosure is a method of manufacturing asemiconductor device. FIGS. 1 to 10 present cross-section views ofselected steps of an example implementation of a method of fabricating asemiconductor device 100 according to the principles of the presentdisclosure. In some embodiments the device 100 includes one or moretransistors (e.g., transistors 102, 104) such as metal-on-oxide (MOS),transistors, such as pMOS or nMOS transistors. The method includesforming at least one of these transistors 102 on a semiconductorsubstrate 105 by a manufacturing process as disclosed herein.

FIG. 1 shows the device 100 after forming an isolation structure 107(e.g., shallow trench isolation or field oxide structure) in or on asemiconductor substrate 105. E.g., forming isolation structures 107 caninclude a dry-etch, wet-etch, or a combination thereof, to form openingsin a silicon substrate 105, followed by depositing an insulator (e.g.,silicon dioxide) in the openings. The substrate 105 can include asilicon layer that is epitaxially grown on a silicon-germaniumsubstrate, or other types of semiconductive material such as indiumphosphide or gallium arsenide. The substrate can be implanted with n- orp-type dopants to form doped wells 110.

FIG. 1 also shows the device 100 after depositing a gate dielectriclayer 115 on the substrate 105, and after depositing asilicon-containing layer 120 (e.g., polysilicon) on the gate dielectriclayer 115. Example insulating materials include plasma nitrided oxide,hafnium oxide, silicon oxide or high-k dielectric materials (e.g.,dielectric constant of 4 or greater). Chemical vapor deposition (CVD),physical layer deposition (PVD), atomic layer deposition (ALD), or otherconventional methods can be used to deposit the layers 115, 120.

FIG. 2 shows the device 100 after forming first and second gates 205,210. Forming the first and second gates 205, 210 can include patterning,in separate or combined steps, the dielectric layer 115 and thesilicon-containing layer 120 (FIG. 1), to form patterned first anddielectric layers 215, 220 and first and second silicon-containingelectrode layers 225, 230, respectively. Forming the first and secondgates 205, 210 can also include forming insulating sidewalls 235 on thevertical walls 240 of the patterned dielectric layers 215, 220 andpatterned silicon-containing layers 225, 230. As illustrated in FIG. 2,a thickness 245 of the patterned first silicon-containing electrodelayer 225 can be substantially the same as a thickness 250 of the secondpatterned silicon-containing electrode layer 230. E.g., both thicknesses245, 250 can equal about 50 to 150 nm±10 percent, and in about 80 to 100nm±10 percent in some cases.

FIG. 3 shows the device 100 after etching simultaneously, the firstpatterned silicon-containing electrode layer 225 of the first gate 205and first substrate portions 305, 310, adjacent to the first gate 205,to form a first gate electrode opening 315 and source and drain openings320, 322 respectively. A portion of the first patternedsilicon-containing electrode layer 225 remains in the first gate 205 atthe conclusion of the simultaneous etch. The thickness 330 of thepatterned and etched first silicon-containing electrode layer 225 isless than the layer's 225 thickness 245 (FIG. 2) before the simultaneousetch. The second gate 210 and second substrate portions 340, 345,adjacent to the second gate 210, are masked during the simultaneousetch. E.g., a mask layer 350 comprising a conventional oxide layer,nitride layer, or both, can be blanket deposited on the substrate 105and then patterned to expose those portions of the at least onetransistor 102 to which the simultaneous etch is then applied.

Some embodiments of the simultaneous etch are configured to be selectivetowards the insulating sidewalls 235 and mask layer 350. E.g., the etchrate of the substrate 105 and first silicon-containing electrode layer225 is at least about 10 times greater than the etch rate of theinsulating sidewalls 235 or mask layer 350. Some embodiments of thesimultaneous etch are configured to remove the substrate 105 andpatterned first silicon-containing electrode layer 225 at substantiallythe same rate. That is, the simultaneous etch removes about the samethickness 355 of the patterned first silicon-containing electrode layer225 as a thickness 360 of substrate 105 removed. E.g., in some cases,the thicknesses 355, 360 removed are both equal to within about 10percent, e.g., about 50 nm±5 nm.

Certain embodiments of the simultaneous etch include exposing the firstgate 205 and first substrate portions to an HBr-containing etchant gas(e.g., a reactive ion etch comprising HBr). Embodiments of thesimultaneous etch can include an isotropic etch and an anisotropic etch.In some cases both the isotropic etch and anisotropic etch comprise HBr.E.g., the simultaneous etch can includes HBr, HCl, combinations thereof,or other conventional substrate etchants.

FIG. 4 shows the device 100 after forming SiGe 405, 410 simultaneouslyin the first gate electrode opening 315 (FIG. 3) and the source anddrain openings 320, 322 respectively. The second gate 210 and secondsubstrate portions 340, 345 adjacent to the second gate 210 are maskedand SiGe 405, 410 is formed in the openings 315, 320, 322 (FIG. 3). Forinstance, the mask layer 350 (e.g., an oxide layer) can be left over thesecond gate 210 and second substrate portions 340, 345. The SiGe 410 inthe source and drain openings 320, 322 form first source and drainstructures 420, 425 that configured to produce a compressive stress inthe channel region 430 of the first transistor 102. The SiGe 405 in thefirst gate electrode opening 315 can also produce a compressive stressin the channel region 430.

Forming the SiGe 405, 410 can include growing SiGe in each of the firstgate electrode opening 315 and source and drain openings 320, 322 untilthe openings 315, 320, 322 are filled with SiGe. An example SiGe 405,410 forming process includes a chemical vapor deposition process havingabout 0 to 50 percent atomic percent Ge at different stages in thedeposition process. E.g., SiGe can be selectively epitaxially grown inthe openings 315, 320, 322 (e.g., grown on silicon surfaces of theopenings 315, 320, 322 to the exclusion of silicon oxide or siliconnitride-covered surfaces on the substrate) using a CVD processcomprising SiH₄, or Si₂H₆, plus GeH₄ and HCl, and optionally B₂H₆. Oneskilled in the art would appreciate that there are a variety ofdifferent ways to grow SiGe in the openings 315, 320, 322.

FIG. 4 also shows the device 100 after masking the second transistor 104(e.g., mask layer 350 in FIG. 3, or a photoresist mask) and implantingdopants 435 into the first source and drain structures 420, 425. E.g.,p-type dopants are implanted when the transistor 102 is a pMOStransistor. Implanting the dopants 435 serves to lower the resistancethe source and drain structures 420, 425. Additionally, either before orafter forming the first source and drain structures 420, 425, the firsttransistor 102 can be masked and dopants 437 implanted into the secondsubstrate portions 340, 345 as part of forming second source and drainstructures 440, 445 of the second transistor 104. E.g., n-type dopantsare implanted when the transistor 104 is an nMOS transistor. One skilledin the art would be familiar with the procedures to mask non-implantedareas, implant dopants, and the means to diffuse the dopants into thesubstrate 105 using conventional processes like rapid thermal or laserannealing.

FIG. 5 shows the device 100 after depositing a sacrificial layer 510 onthe substrate 105, where the first and second gates 205, 210 are coveredby the PMD layer 510. E.g., after removing the mask layer 350 (FIG. 3),a sacrificial layer 510 layer comprising an insulating layer 515composed of silicon dioxide, tetra-ethyl-ortho-silicate (TEOS), orsimilar material can be deposited by CVD. Depositing the sacrificiallayer 510 can further include depositing a nitride layer 520 (e.g.,silicon nitride layer) using CVD.

FIGS. 6 and 7 show the device 100 at selected stages of removing theSiGe 405 from the first gate 205. FIG. 6 shows the device 100 afteruncovering upper surfaces 610, 620 (e.g., the surfaces facing away fromthe substrate) of first and second gates 205, 210. Uncovering the uppersurfaces 610 can include a CMP process. E.g., in some cases the CMPprocess includes the use of a polishing pad and slurry that planarizesthe insulating layer 515 of the sacrificial layer 510 and stops on thenitride layer 520. Portions of the nitride layer 520 that lay directlyon the upper surfaces 610, 620 can then be removed using an etchingprocedure, e.g., a plasma etch. In other cases, however, both of theinsulating layer 515 and nitride layer 520 that are over the uppersurfaces 610, 620 can be removed by the CMP process, which can comprisesingle or multiple polishing steps. As illustrated in FIG. 6 the uppersurfaces 610, 620 of the gates 205, 210 can be coplanar with theuppermost surface 630 of CMP planarized sacrificial layer 510. As alsoillustrated, the SiGe-filled the source and drain openings 320, 322remained covered by the sacrificial layer 510.

FIG. 7 shows the device 100 after subjecting the upper surfaces 610, 620of the gates 205, 210 (FIG. 6) to an etch process to thereby selectivelyremove the SiGe 405 (FIG. 6) from the first gate 205 and form a secondgate electrode opening 710 therein. In some cases, the second gateelectrode opening 710 is substantially the same in size as the firstgate electrode opening 315 (FIG. 3). That is, substantially all of theSiGe 405 is removed (e.g., at least about 99 percent) from the firstgate 205, while the sidewalls 235 and remaining portion of the firstpatterned silicon-containing electrode layer 225 are left substantiallyunaltered by the SiGe removal etch process. E.g., the etch rate of theSiGe 405 (FIG. 6) is at least about 100 times greater than the etch rateof the insulating sidewalls 235 or of the first patternedsilicon-containing electrode layer 225 that remains in the first gate205.

In some cases, the SiGe removal etch is selective to the second gate210. That is, the process for removing the SiGe 405 from the first gate205 leaves the second gate 210 substantially unaltered. E.g., theremoval rate of the second patterned silicon-containing electrode layer230 is less than about 10 percent, and in some cases, less than about 1percent, of the removal rate of the SiGe 405 of the first gate 205. Someembodiments of the selective etch process comprise a wet etch comprisingNH₄OH, H₂O₂ and H₂O. E.g., the etch process can be a wet etch using amixture of NH₄OH:H₂O₂:H₂O in ratios of about 1:1:5, respectively.

In other cases, however, the etch process is not selective. Rather, thesecond gate 210 is covered with a mask (e.g., a mask similar to the masklayer 350 depicted in FIG. 3) to prevent the undesired removal of thesecond patterned silicon-containing electrode layer 230 while removingthe SiGe 405 from the first gate 205. As further illustrated in FIG. 7,removing the SiGe 405 from the first gate 205 also leaves theSiGe-filled source and drain structures 420, 425 substantially unalteredbecause these structures 420, 425 are covered by the sacrificial layer510.

FIG. 8 shows the device 100 after depositing a metal 805 simultaneouslyon the first and second gates 205, 210 to form a metal layer 810thereon. The metal layer 810 can be deposited directly on the patternedfirst and second silicon-containing layers 225, 230. In some cases, themetal layer includes a refractory metal such as nickel, deposited byconventional means (e.g., a PVD process).

Substantially the same thickness 820 of metal layer 810 is deposited onthe first and second gates 205, 210 in a single metal deposition step.As illustrated in FIG. 8, sufficient amounts of the metal can bedeposited so as to fill the second gate electrode opening 710 (FIG. 7).However, because a portion of the silicon-containing layer of the firstgate 205 was previously removed (FIG. 3), the first and second gates205, 210 have different thickness ratios of the metal layer 810 to thepatterned first and second silicon-containing layers 225, 230.

For instance, a ratio of the thickness 820 of the metal layer 810 to thethickness 330 (FIG. 3) of the patterned and etched firstsilicon-containing layer 225 is greater than a ratio of the thickness820 of the metal layer 810 to the thickness 250 (FIG. 2) of thepatterned second silicon-containing layer 230. E.g., a ratio of thethickness 820 of the metal layer 810 to a thickness 330 of thesilicon-containing layer 225 for the first gate 205 ranges from about2:1 to 3:1. E.g., a ratio of a thickness 820 of the metal layer 810 to athickness 250 of the silicon-containing layer 230 for the second gateelectrode 210 ranges from about 0.9:1 to 1.1:1.

FIG. 9 shows the device 100 after annealing the first and second gates205, 210 to form fully silicided first and second gates electrodes 910,920. That is, the materials of the first patterned silicon-containingelectrode layer 225 and the metal layer 810 (FIG. 8) are heated to atemperature that is sufficient to inter-diffuse the atoms of the firstpatterned silicon-containing electrode layers 225 and the metal layer810 to form the first fully silicided electrode layer 910. Similarly,the anneal causes the second patterned silicon-containing electrodelayers 225 and the metal layer 810 to inter-diffuse to form the secondfully silicided electrode layer 920.

FIG. 9 shows that the fully silicided first and second gates electrodes910, 920 can protrude above the uppermost surface 630 of the planarizedsacrificial layer 510. This follows because the volume occupied by themetal-silicide crystal structure of the fully silicided first and secondgates electrodes 910, 920 can be greater than the sum of the volumes ofsilicon-containing electrode layers 225, 230 and the metal layer 810(FIG. 8) that the electrode 910, 920 were formed from. E.g., theformation of electrodes 910, 920 comprising NiSi, Ni₂Si, Ni₃₁Si₁₂,Ni₃Si, or mixed phase crystals of Ni and Si, will cause an expansivestress on the gate's 205, 210 sidewalls 235, which could potentiallydelaminate the sidewalls 235 from the electrodes 910, 920.

In some embodiments, the anneal includes a first anneal having anuppermost temperature of about 400° C. and a second anneal having anuppermost temperature of about 500° C. E.g., is some cases the annealincludes a first anneal to a temperature of about 320 to 400° C. forabout 30 to 60 seconds, followed by a second anneal to a temperature ofabout 400 to 500° C. for about 60 seconds. In some embodiments the firstanneal is sufficient to fully diffuse the atoms of the first patternedsilicon-containing electrode layers 225 and the metal layer 810 to forma homogenous fully silicided first gate electrodes 910. Consequently,the second anneal does not substantially change the distribution ofatoms (e.g., Ni and Si atoms) in the fully silicided first gateelectrodes 910. In such instances the second anneal serves to furtherdiffuse the atoms of the second patterned silicon-containing electrodelayers 230 and the metal layer 810.

In some cases, portions 930 of the metal layer 810 do not interdiffusewith the patterned first and second silicon-containing layers 225, 230(FIG. 8). This unreacted metal layer portion 930 can be removed usingconventional procedures before conducting additional devicemanufacturing steps. E.g., removing the unreacted metal layer portion930 of nickel can include exposure to a solution of H₂SO₄:H₂O₂ in a 6:1ratio. In some embodiments the unreacted metal portion 930 is removedbetween the first and second anneals.

An amount of the metal 805 (FIG. 8) at an interface 940 of the fullysilicided gate electrode layer 910 and an underlying gate dielectriclayer 215 is greater than an amount of the metal 805 an second interface950 of the second fully silicided gate electrode layer 920 and anunderlying second gate dielectric layer 220. In some instance, theamount of the metal 805 in the fully silicided first gate electrode 910is greater than an amount of the metal 805 in the fully silicided secondgate electrode 920. E.g., there can be a greater amount of nickel in thefully silicided first gate electrode layer 910 than in the fullysilicided second gate electrode layer 920. In some cases, the fullysilicided first gate electrode 910 comprises Ni₂Si while the fullysilicided second gate electrode layer 920 comprises NiSi. E.g., therecan be Ni₂Si and NiSi at the respective interfaces 940, 950 of the gates205, 210. In other cases, the fully silicided first gate electrode 910comprises Ni₃Si or Ni₃₁Si₁₂, while the fully silicided second gateelectrode layer 920 comprises NiSi (e.g., Ni₃Si or Ni₃₁Si₁₂ at theinterface 940 and NiSi at the second interface 950). A fully silicidedfirst gate electrode 910 comprising Ni₃Si or Ni₃₁Si₁₂ at the interface940 has a higher work function than a fully silicided first gateelectrode 910 comprising Ni₂Si at the second interface 950 A fullysilicided first gate electrode 910 comprising Ni₂Si, however, willimpart less expansive stress on the first gate's 205 sidewalls 235 thanNi₃Si. In some cases, a fully silicided first gate electrode 910comprising Ni₃₁Si₁₂ provide a suitable combination of high work functionplus an acceptable level expansive stress.

One skilled in the art would appreciate that there can be multipleadditional manufacturing steps to complete the fabrication of the device100. E.g., as illustrated in FIG. 10, for embodiments of the device 100configured as an integrated circuit, the method can include conventionalprocesses to remove the sacrificial layer 510 (FIG. 9), and form formedmetal silicide electrodes 1005 on the source and drain structures 420,425, 440, 445, and gate electrodes 910, 920. Thereafter a pre-metalnitride layer 1010 and pre-metal dielectric (PMD) layer 1015 can bedeposited on the substrate 105. One or more inter-level dielectriclayers (IDL) 1020 can then be deposited on the pre-metal dielectriclayer 1015. As further illustrated, interconnects 1025 can be formedthrough the ILD layers 1010 and PMD layer 1005. The interconnects 1025can include metal contacts, lines, single or dual damascene structures,comprising tungsten, copper, or other metals. Certain interconnects 1025contact conventionally formed metal silicide electrodes 1005 located onthe source and drain structures 420, 425, 440, 445, and gate electrodes910, 920, to thereby interconnect the transistors 102 to each other, orto other transistors 104 of the integrated circuit. E.g., the first andsecond transistors 102, 104, configured as pMOS and nMOS transistors,respectively, can be interconnected to form a complementary MOS (CMOS)device 1027.

FIG. 10 illustrates another embodiment, a semiconductor device 100. Inthis example, the device 100 is configured as an integrated circuit. Theintegrated circuit 100 can comprise one or more transistors 102, 104 onor in the semiconductor substrate 105. At least one of the transistors102 includes a gate 205 having a fully silicided gate electrode layer910 with a ratio of Ni:Si that ranges from about 2:1 to 3:1. Thetransistor 102 also includes source and drain structures 420, 425located in openings 320, 322 of the substrate 105 and adjacent to thegate 205, wherein the source and drain structures 420, 425 are filledwith SiGe.

As a consequence of performing the anneal as discussed in the context ofFIG. 9, the gate 205 has an interface 940 that corresponds to thatportion of the first fully silicided electrode layer 910 that directlycontacts the first patterned gate dielectric layer 215. In someembodiments, the ratio of Ni to Si (Ni:Si) at the interface 940 equalsabout 2:1. In other embodiments, the Ni:Si ratio at the interface 940equals about 3:1.

As further illustrated in FIG. 10 the device 100 configured as anintegrated circuit can further include a second transistor 104. Thesecond transistor 104 comprises a second gate 210 having a fullysilicided second gate electrode layer 920. Similar to the first gate205, the second gate 210 has a second interface 950. A ratio of Ni:Si atthe second interface 950 ranges from about 0.9:1 to 1.1:1. The secondtransistor 104 also includes second source and drain structures 440, 445located in the substrate 105 and adjacent to the second gate 210,wherein the second source and drain structures 440, 445 are free ofSiGe.

The different Ni:Si ratios at the interface 940 and second interface 950facilitates the work function of the first transistor 102 and secondtransistor 104 to be different from each other. E.g., at least about 0.3eV different in some cases, and about 0.8 eV in other cases. E.g., insome embodiments, the work function of the first transistor 102configured as a pMOS transistor can range from about 4.8 to 5.0 eV. Thework function of the second transistor 104 configured as an nMOStransistor can range from about 4.2 to 4.5 eV.

In some embodiments, the Ni:Si ratio in the second fully silicided gateelectrode 920 increases from the second interface 950 to the uppersurface 620 of the second gate 210. E.g., in some cases there is acontinuously increasing gradient of Ni:Si from about 1:1 at the secondinterface 950 to about 2:1 or greater at the upper surface 620 of thefully silicided second gate electrode layer 920. This is in contrast tothe first fully silicided gate electrode 910, which in the sameembodiment, can have a uniform Ni to Si ratio from the interface 940 tothe upper surface 610 of the first gate 210. E.g., the Ni:Si ratiochanges by less than 10 percent from the interface 940 to the uppersurface 610.

As discussed in the context of FIG. 4, in some embodiments, the secondsource and drain structures 440, 445 are not formed in openings of thesubstrate 105. Rather, the second source and drain structures 440, 445can be formed by implanting dopants into the substrate 105 and annealingthe substrates 105 to diffuse the dopants. In other cases, however, thesecond source and drain structures 440, 445 can be formed by formingopenings in the substrate 105 and filing the openings with a strainproducing material other than SiGe, e.g., SiC.

Those skilled in the art to which the invention relates will appreciatethat other and further additions, deletions, substitutions andmodifications may be made to the described example embodiments, withoutdeparting from the invention.

1. An integrated circuit, comprising: one or more transistors on or in asemiconductor substrate, wherein at least one of said transistorsincludes: a gate having a fully silicided gate electrode layer with aratio of Ni:Si ranging from about 2:1 to 3:1; and source and drainstructures located in openings of said substrate and adjacent to saidgate, wherein said source and drain structures are filled with SiGe. 2.The circuit of claim 1, wherein said ratio equals about 2:1 at aninterface of said fully silicided gate electrode layer and an underlyinggate dielectric layer.
 3. The circuit of claim 1, wherein said ratioequals about 3:1 at an interface of said fully silicided gate electrodelayer and an underlying gate dielectric layer.
 4. The circuit of claim1, further including a second transistor including: a second gate havinga fully silicided second gate electrode layer, wherein a secondinterface of said fully silicided second gate electrode layer and anunderlying second dielectric layer has a second ratio of Ni:Si rangingfrom about to 1.1:1; and second source and drain structures in saidsubstrate and adjacent to said second gate, wherein said source anddrain structures are free of SiGe.
 5. The circuit of claim 4, whereinsaid second ratio increases from said second interface to an uppersurface of said second gate.